The present invention relates to a method and apparatus for use in tests of circuit chips, and more particularly relates to a method and apparatus for making connections between circuit chips and a temporary carrier for use in conducting burn-in tests of the circuit chips.
Semiconductor devices are becoming smaller and more dense with the evolution of new technology. However, increases in circuit density produce a corresponding increase in overall chip failure rates at a time when chip failure rates must decrease to remain competitive. Chip manufacturers are therefore challenged to improve the quality of their products by identifying and eliminating defects which produce defective chips known as fails. Whereas significant improvements are being made to eliminate systematic defects by reducing process variability, process improvements alone are not sufficient to eliminate all the random defects which affect both yield and reliability. Historically, screening techniques have been employed to improve product failure rates to acceptable levels by culling out many of these random defects.
The most successful of these screen types is burn-in, which has also seen significant improvement in recent years. When static burn-in was first introduced, failure rate improvement factors of 2 were typical for bipolar and early MOSFET products. Dynamic burn-in involving the application of stimuli to chip input/output pads yields a 5 to 20X improvement. It is now known that the efficiency of burn-in is limited by fails which escape detection during the burn-in process. Some chips see incomplete or no burn-in and account for many of the early fails experienced during use.
In situ burn-in was developed to overcome this deficiency. During in situ burn-in, tests are performed to ensure that the chips are experiencing proper stress, and fails which have the potential to recover are identified. In situ burn-in has been shown to improve failure rates by a factor of 30 or more. For single-chip modules, the burn-in process usually involves the insertion of the fully packaged chip into a socket on a burn-in board. For multi-chip modules (MCM's) the process is generally not as straightforward; with mixed technologies on the same MCM, the situation becomes even more complex. CMOS chips used in a multi-chip package along with bipolar chips cannot use the in situ burn-in process necessary to achieve the reliability objectives.
For high density chips, the best and most efficient way to improve the reliability failure rates is through in situ burn-in of the single chip module. Chips are placed on ceramic substrates using a solder reflow chip joining process and then are capped, tested, burned-in and shipped to the customer.
Reusable Chip Test Package, Bry et al, IBM Technical Disclosure Bulletin, Vol. 22, No. 4, Sept. 1979, discloses a test package which permits the mounting of an integrated circuit chip without the use of solder or other kind of bonding for testing prior to final encapsulation.
Dynamic Burn-In of Integrated Circuit Chips at the Wafer Level, IBM Technical Disclosure Bulletin, Vol. 29, No. 6, November 1986 discloses a burn-in test at the wafer level wherein a wafer is attached to and removed from a printed circuit board by a radiant heat source.
Improved Semiconductor Chip Solder Ball to Minimize Stress, 29111, Research Disclosure, July 1988, Number 291, discloses making a permanent connection between a chip solder ball and substrate which is personalized by a solder dam over the substrate having holes therein at a chip pad site for making connections therethrough.
Test and Repair of Direct Chip Attach Modules, IBM Technical Disclosure Bulletin, Vol. 31, No. 3, August 1988, discloses a method for removing a chip from a module where the chip tests bad or the joint between a module pad and a chip connection is bad. In the disclosed method, the chip is destroyed in the removal process, and a new chip attached.
Solder Ball Reflow, 30239, Research Disclosure, June 1989, No. 302 discloses making a permanent connection between a solder ball and a metal pad on a ceramic circuit substrate by superpositioning on the substrate, a plate fixture to which solder does not adhere. The plate has openings which restrain the solder balls so that they flatten and reach respective pads and pins during reflow.
U.S. Pat. No. 4,975,079 for Connector Assembly for Chip Testing, issued Dec. 4, 1990 to Beaman et al, discloses an electrical connector having contact members and urging means for making electrical contact with convex deformable contact areas on an electric device during a test.